1. Field of the Invention
The present invention generally relates to a method of manufacturing a semiconductor field effect device, and more particularly, to a method of manufacturing a semiconductor device having both a channel stop and channel impurity regions formed in a well, wherein the number of masking steps is minimized. The invention further relates to a semiconductor device formed thereby.
2. Description of the Background Art
A typical example of a semiconductor device in which a well is formed on a semiconductor substrate and a transistor is formed on the main surface of the well is a complimentary MOS transistor (hereinafter referred to as a CMOS transistor). The CMOS transistor is characterized in that an n channel MOS transistor and a p channel MOS transistor exist together. An advantage of the CMOS transistor is that power consumption is extremely small because a DC voltage between the power supply terminals is very small.
Meanwhile, an important step during the processing of a CMOS structure is a well forming technique. In order to make an NMOS and a PMOS on the same semiconductor substrate, regions for each of elements should be isolated. More specifically, a P well region for an N channel element and an N well region for a P channel element should be provided.
Referring to drawings, a description is given of a conventional technique of forming a well.
FIGS. 9A to 9T are sectional views of a conventional CMOS transistor showing its manufacturing steps.
Referring to FIG. 9A, an oxide film 2 and a nitride film 3 are sequentially formed on a semiconductor substrate 1 (for example a silicon substrate). Then, a resist 4 is applied to the whole surface of the semiconductor substrate 1.
Referring to FIG. 9B, the resist 4 is patterned so as to expose the portion in which the N well is to be formed. The nitride film 3 is patterned using this patterned resist 4 as a mask. Then, impurities for forming the N well, for example phosphorus are implanted using the patterned resist 4 as a mask. Thereafter, the resist 4 is removed.
Referring to FIG. 9C, a thick isolation oxide film 2a is selectively formed on a portion of the semiconductor substrate 1 using the nitride film 3 as a mask. Thereafter, the nitride film 3 is removed.
Referring to FIG. 9D, impurities for forming the P well, for example boron are implanted to the whole surface. Then, referring to FIG. 9E, heat treatment (6.about.8 hours) for diffusing the impurities for forming the well deeply is performed. Thereafter, referring to FIG. 9F, the isolation oxide film 2a is removed and the semiconductor substrate 1 on which an N well 5 and P well 6 were formed is obtained.
Referring to FIG. 9G, an oxide film 7, a nitride film 8 and a resist 9 are sequentially formed on the main surface of the semiconductor substrate 1. Then, referring to FIG. 9H, in order to define an active region, the resist 9 is patterned by photolithography such that the pattern resist 9 may remain on the upper portion of the active region. Thereafter, the nitride film 8 is patterned using the patterned resist 9 as a mask. Then, a resist is formed (not shown) on the whole surface of the semiconductor substrate 1 comprising the patterned resist 9.
Then, referring to FIG. 9I, the resist 10 is patterned such that the pattern of the resist 10 may remain on the N well region 5. Thereafter, boron ions which are the same as that forming the P well 6 are implanted in a non-active region to form an isolation portion 11. The reason why boron is implanted in the non-active region is that, although a thick isolation oxide film is formed at the non-active region for forming the active region in the next step, impurity boron forming the P well is absorbed in the isolation oxide film, so that the concentration of boron at the non-active region becomes low. When the concentration of boron becomes low, a phenomenon called a latch-up is generated. When the latch-up occurs, the N channel element will not be isolated. The latch-up phenomenon is described in detail in an article "VLSI TECHNOLOGY"(S. M. Sze, McGraw Hill International Book Company). Therefore, the isolation process in which boron is implanted in the non-active region to form the isolation portions 11 is necessary. After the isolation process, the patterns of the resists 9 and 10 are removed.
Referring to FIG. 9J, heat oxidation is carried out using the pattern of the nitride film 8 as a mask to form a thick isolation oxide film 7a at the non-active region. Thereafter, the nitride film 8 is removed to obtain the semiconductor substrate 1 on which the active region is defined.
Referring to FIG. 9K, a pattern of the resist 12 is formed by photolithography on the N well region 5. Thereafter, ions of boron are implanted in a channel region 13 of an MOS transistor to be formed on the P well 6. The purpose of the ion implantation into the channel region 13 is to optimize a threshold voltage of the MOS transistor and to prevent a punch through. The punch through means that a depletion layer of a drain extends to the channel portion as the voltage of the drain is raised and is finally connected to the source region, with the result that a current cannot be controlled by the gate voltage. Thereafter, the pattern of the resist 12 is removed.
Referring to FIG. 9L, the pattern of the resist 14 is formed on the P well region 6 by photolithography. Thereafter, ions of boron and arsenic are implanted in the channel region 15 of the MOS transistor to be formed in the N well 5 using the pattern of the resist 14 as a mask. Boron is thus used to balance the threshold voltages both of the respective transistors formed on the P well 6 and the N well 5.
Then, referring to FIG. 9M, the pattern of the resist 14 is removed. Referring to FIG. 9N, a thin oxide film 7b formed on the active region is removed.
Referring to FIG. 90, gate oxide films 50 are formed on the main surfaces of the wells 5 and 6. Thereafter, a polysilicon layer 16 serving as a gate electrode is formed on the whole surface of the semiconductor substrate 1 comprising the gate oxide films 50.
Then, referring to FIG. 9P, the polysilicon layer 16 is patterned to form a gate electrode 17 on the N well 5 and a gate electrode 18 on the P well 6.
Referring to FIG. 9Q, the P well 6 is covered with the pattern of the resist 19 and ions of boron is implanted in the N well 5 using the patter of the resist 19 as a mask. As a result, source/drain regions 20 are formed in the N well 5 and a p channel MOSFET is formed. Then, the pattern of the resist 19 is removed.
Referring to FIG. 9R, the N well 5 is covered with the pattern of the resist 21 and ions of arsenic are implanted in the P well 6 using this pattern of the resist 21 as a mask. As a result, source/drain regions 22 are formed in the P well 6 and an n channel MOSFET is formed. Thereafter, the pattern of the resist 21 is removed.
Then, referring to FIG. 9S, an insulating film 23 comprising SiO.sub.2 is formed on the whole surface of the semiconductor substrate 1 comprising the gate electrodes 17 and 18.
Referring to FIG. 9T, a contact hole 39 is provided in the insulating film 23 and wiring is carried out with an aluminum metal 24, with the result that a CMOSFET is completed.
The conventional manufacturing method of the CMOSFET is thus structured. However, there was a disadvantage as follows.
That is, in the conventional example shown in FIGS. 9A to 9T, referring to FIG. 9E, heat treatment for a long time of 6.about.8 hours was necessary for diffusing the impurity ions (for forming the well) into the semiconductor substrate 1. In addition, in this conventional example, referring to FIGS. 9B, 9H, 9I, 9K and 9L, five photolithography processes were necessary before the state shown in FIG. 9N was implemented.
FIG. 10 shows another conventional example of a method of manufacturing the CMOSFET disclosed in Japanese Patent Laying-Open Gazette No. 63-192268. In this conventional example, referring to FIG. 10, there is disclosed a technique of forming a well region 26 on the semiconductor substrate 1 by implanting ions of impurities for forming a well (B.sup.+ ions) in the semiconductor substrate 1. In addition, according to the conventional example, the well region 26 and a channel stopper region 25 are formed at the same time by using a mask 27 of a specific configuration.
In the conventional example shown in FIG. 6, since impurities are not implanted in the channel region, there is a disadvantage that punch through of the transistor formed as described is generated. In addition, it was difficult to form a mask 27 having such shape as shown in the figure.